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Ordering number : ENA0599
Monolithic Linear IC
LA6560
Overview
For CD
Five-Channel Driver (BTL : Four-Channel, H Bridge : One-Channel)
The LA6560 is a 5-channel driver (BTL : 4-channel, H bridge : 1-channel) for CD players.
Functions
* Power amplifier 5-channel built-in. (Bridge-connection (BTL) : 4-channel, H bridge : 1-channel) * IO max 1A * Level shift circuit built-in (except H bridge). * Mute circuit (output ON/OFF) built-in. (Operable with BTL AMP and not operable for the H bridge of 5VREG) * 5V regulator built-in (external PNP transistor). * With VREF changeover function (H : external, L : internal (2.5V) selected) * Overheat protection circuit (thermal shutdown) built-in.
Specifications
Maximum Ratings at Ta = 25C
Parameter Supply voltage Allowable power dissipation Symbol VCC max Pd max Independent IC Mounted on specified board. * Maximum output current Maximum input voltage MUTE pin voltage Operating temperature Storage temperature * Specified board size : 76.1x114.3x1.6mm3, IO max VINB VMUTE Topr Tstg glass epoxy. Each output for H bridge, channel 1 to 4. Conditions Ratings 14 2.0 0.8 1 13 13 -30 to +85 -55 to +150 Unit V W W A V V C C
Recommended Operating Conditions at Ta = 25C
Parameter Supply voltage Symbol VCC Conditions Ratings 5.6 to 13 Unit V
Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.
D0606 MS PC B8-6307 No.A0599-1/9
LA6560
Electrical Characteristics at Ta = 25C, VCC1 = VCC2 = 8V, VREF = 2.5V, unless especially specified.
Parameter ALL Blocks No-load current drain ON No-load current drain OFF Thermal shutdown temperature VREF AMP VREF-AMP offset voltage VREF Input voltage range VREF-OUT output current BTL AMP Block (CH1 to CH4) Output offset voltage Input voltage range Output voltage VOFF VIN VO VG SR VMUTE-ON VMUTE-OFF Voltage difference between outputs for BTL AMP, each channel. *2 Input voltage range for input for OP-AMP. Each voltage between V0+ and V0- when RL = 8. *3 Closed-circuit voltage gain Slew rate MUTE ON voltage MUTE OFF voltage Input AMP Block (CH1 to 4) Input voltage range Output current (SINK) Output current (SOURCE) Output offset voltage CH1 input changeover voltage 1 CH1 input changeover voltage 2 Loading Block (CH5, H bridge) Output voltage VO-LOAD VCE-BREAK VIN-L VIN-H At forward and reverse rotation, RL = 8, VCONT=VCC *3 Break output saturation voltage Input low level Input high level Output voltage at braking *7 0.3 1 2 V V V 5.7 6.5 V VIN-OP SINK-OP SOURCE-OP VOFF-OP VSW-OP1 VSW-OP2 CH1 input AMP(B), external REF select *6 CH1 input AMP(A), internal VREF select *6 *5 0 2 300 -10 2 0.5 500 10 VCC-1.5 V mA A mV V V Input and output gain. Input OP-AMP:BUFFER AMP Independent Multiply 2 between outputs. Output ON voltage, each MUTE *4 Output OFF voltage, each MUTE *4 2 0.5 V V 0.5 V/s 3.6 4 4.4 Times 0 5.7 6.2 VCC-1.5 mA V -50 50 mV VREF-OFFSET VREF-IN I-VREF-OUT CH1 input reference voltage -10 1 2 5 10 VCC-1.5 6.6 mV V mA ICC-ON ICC-OFF TSD BTL-AMP output ON, LOADING block OFF *1 All outputs OFF *1 Design guarantee value 150 10 175 15 200 mA C 30 50 mA Symbol Conditions min Ratings typ max Unit
Power Supply Block (PNP transistor : 2SB632K-use) 5V supply voltage REG-IN SINK current Line regulation Load regulation VOUT REG-IN-SINK VOLN VOLD IO = 200mA Base current of external PNP *8 6V VCC 12V, IO = 200mA 5mA IO 200mA 4.8 5 5.0 10 10 10 100 100 5.2 V mA mV mV
Note *1 : Current dissipation that is a sum of VCC1 and VCC2 at no load. *2 : Input AMP is a BUFFER AMP. *3 : Voltage difference between both ends of load (8). Output saturated. *4 : Output ON with MUTE : [H] and OFF with MUTE : [L] (HI impedance). *5 : The source of input OP-AMP is a constant current. As the 11k resistance to the next stage is a load, pay due attention when setting the input OP-AMP gain. *6 : With VIN1-SW : [L], the input AMP selects AMP-A while VREF selects internal VREF ( 2.5V). With VIN1-SW : [H], the input AMP selects AMP-B while VREF selects external VREF ( VREF-IN). *7 : Short (GND) brake used. SINK side output ON. *8 : 5VREG incorporates a drooping protection circuit and operated when the base current is 10mA (TYP).
No.A0599-2/9
LA6560
Package Dimensions
unit : mm (typ) 3251
17.8 (6.2) 36 19
(4.9) 7.9 10.5
(0.5)
1
0.8
2.0
0.3
18 0.25
(2.25)
2.7
SANYO : HSOP36R(375mil)
0.1
2.45max
0.65
2.5
Pd max -- Ta
Specified board : 76.1x114.3x1.6mm3 glass epoxy When mounted on a board
Allowable power dissipation, Pd max - W
2
1.5
1 0.8 0.5
1.04
Independent IC
0.42
0 --30 --20
0
20
40
60
80
100
Ambient temperature, Ta - C
No.A0599-3/9
LA6560
Block Diagram
Input
FWD
1
Signal system GND Thermal shutdown (LOAD output voltage setting)
36
S-GND
REV
2
35
VCONT
VCC2 VLO-
3
Output control
BTL-AMP Output ON/OFF
MUTE
34
MUTE
4
33 22k 11k
VIN4 VIN4VIN4+ VREF-IN
VLO+
5
32
VO4+ VO4VO3+ VO3-
6
Level shift
31
7
30
Level shift
8
VIN1/VREF-SW
29
VIN1(VREF)-SW VREF-OUT(CH1)
9 Power system GND
28
FR FR
Power system GND 5VREG (Extemal PNP)
Level shift
FR FR
VO2+ 10 VO2- 11 VO1+ 12 VO1- 13 VCC1 14
27
REG-OUT
26 22k 11k
REG-IN
Level shift
25
VIN3+ VIN3VIN3 VIN2+ VIN2VIN2 VIN1+B
24
23 22k 11k 22k 11k
VIN1 15 VIN1-A 16 AMP-A VIN1+A 17 VIN1-B 18 AMP-B
22
[L]
[H] VIN1 (VREF)-SW [L]:Internal VREF (2.5V fixed) [H]:Internal VREF
21
20
VIN1 (VREF)-SW [L]:AMP-A [H]:AMP-B
19
No.A0599-4/9
LA6560
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol FWD REV VCC2 VLOVLO+ VO4+ VO4VO3+ VO3VO2+ VO2VO1+ VO1VCC1 VIN1 VIN1-A VIN1+A VIN1-B VIN1+B VIN2 VIN2VIN2+ VIN3 VIN3VIN3+ REG-IN REG-OUT VREF-OUT VIN1 (VREF) -SW VREF-IN VIN4+ VIN4VIN4 MUTE VCONT S-GND Pin descriptions Output change pin (FWD) for 5CH (VLO), logic input for loading block. Output change pin (REV) for 5CH (VLO), logic input for loading block. Power supply for CH3, 4, and 5. Loading output (-) Loading output (+) Output pin (+) for channel 4 Output pin (-) for channel 4 Output pin (+) for channel 3 Output pin (-) for channel 3 Output pin (+) for channel 2 Output pin (-) for channel 2 Output pin (+) for channel 1 Output pin (-) for channel 1 Power supply for CH1, 2 (BTL). Input pin for channel 1 OP-AMP input AMP-A input pin (-) OP-AMP input AMP-A input pin (+) Input AMP-B input pin (-) for channel 1 Input AMP-B input pin (+) for channel 1 Input pin for channel 2, input AMP output Input pin (-) for channel 2 Input pin (+) for channel 2 Input pin for channel 3, input AMP output Input pin (-) for channel 3 Input pin (+) for channel 3 PNP transistor base connected 5V power output to which the PNP transistor collector connected. CH1 reference voltage output. Outputs internal VREF (2.5V : TYP) or external VREF. Pin for changeover between input AMP-A/internal VREF (TYP2.5V) and input AMP-B/ external VREF. Reference voltage applied pin Input pin (+) for channel 4 Input pin (-) for channel 4 Input pin for channel 4, input AMP output All BTL AMP output ON/OFF LOADING output voltage setting Signal system GND
Note : Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with S-GND.
No.A0599-5/9
LA6560
Pin Description
Pin No. 17 19 16 18 15 22 21 20 25 24 23 32 31 33 1 2 Symbol VIN1+A VIN1+B VIN1-A VIN1-B VIN1 VIN2+ VIN2VIN2 VIN3+ VIN3VIN3 VIN4VIN4+ VIN4 FWD REV Input (H bridge) Logic input pin. By combining H and L of this pin, any one of four modes (forward/ reversed/brake/idling) can be selected. Pin function Input (CH1 to 4) Description Input pin (CH1 to 4) Equivalent circuit
VCC
VIN*-
VIN*
VIN*+
S-GND
FWD 50k 50k S-GND 50k 50k
REV
12 13 10 11 8 9 6 7 4 5 35
VO1+ VO1VO2+ VO2VO3+ VO3VO4+ VO4VLOVLO+ VCONT
Output (BTL-AMP)
Output for channel 1 to 4.
VCC*
VO* RF*
Output (H bridge) H bridge (LOADING) output and LOADING output setting pin
VLO+ VCC
VLO-
P-GND 20k 1k
34 MUTE MUTE BTL AMP output, which turns ON/OFF the output, MUTE : H Output OFF MUTE : L Output OFF
1k 20k
VCONT
VCC1
MUTE 100k 100k S-GND
No.A0599-6/9
LA6560
Truth Table (loading (H bridge) section)
FWD L REV L H H L H VLO+ OFF H L L VLOOFF L H L Loading output OFF *1 Forward Reversed (Short) brake *2
*1 *2
The output has a high impedance. At brake, the SINK side transistor is ON (short brake). VLO+ and VLO- are approximately on the GND level.
Relation of MUTE and Power (VCC*)
CH1(BTL) VCC1 CH2(BTL) MUTE CH3(BTL) CH4(BTL) CH5 (H bridge) VCC2
VIN1 (VREF)-SW (CH1 input AMP selection and internal/external VREF selection function) (Relation between input AMP (CH1 only) and VREF)
VIN1_SW H L Input AMP (CH1) state VIN1-A (AMP-A) VIN1-B (AMP-B) VREF state Internal VREF (2.5V : TYP) External VREF
Internal reference voltage (2.5V (TYP)) VIN1-A
External reference voltage VIN1-B
VREF (VIN1)-SW 0.5V 2V
On MUTE
MUTE L H BTLAMP output OFF ON VREF-OUT operates in an interlock with MUTE. VREF-OUT
No.A0599-7/9
LA6560
Sample Application Circuit
SW MUTE 1 LOADING 2 ELEVETOR 0.1F LOADING MOTOR M 2.2 0.1F TRACKING COIL 2.2 0.1F FOCUS COIL 2.2 9 VO3VREF-OUT(CH1) 28 7 8 VO4VO3+ VREF-IN 30 VIN1(VREF)-SW 29 5 6 VLO+ VO4+ VIN4- 32 VIN4+ 31 3 4 REV VCC2 VLOVCONT 35 MUTE 34 VIN4 33 FWD S-GND 36
FR FR
FR FR
0.1F SPINDLE MOTOR M 2.2 0.1F SLED MOTOR VCC M 2.2
10 VO2+ 11 VO212 VO1+ 13 VO114 VCC1 15 VIN1 16 VIN1-A 17 VIN1+A 18 VIN1-B
REG-OUT 27 REG-IN 26
5VREG
VCC VIN3+ 25 VIN3- 24 VIN3 23 VIN2+ 22 VIN2- 21 VIN2 20 VIN1+B 19
TRACKING FOCUS SPINDLE SLED VREF
No.A0599-8/9
LA6560
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 2006. Specifications and information herein are subject to change without notice. PS No.A0599-9/9

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